Design Verification Engineer - Power Management (Early Career or Experienced)

This role involves enabling bug-free first silicon for mixed-signal designs, working closely with Digital and Analog Design engineers. You will be involved in all phases of pre-silicon verification, including establishing design verification methodology, test-plan development, verification environment development (stimulus and checkers), test-writing, debug, coverage, and sign-off for RTL freeze and tape-out.

Responsibilities

• Develop verification plans in coordination with design leads and architects.
• Build and maintain verification test bench components and environments.
• Generate directed and constrained random tests.
• Run simulations and debug design and environment issues.
• Build functional coverage points, analyze coverage, and improve test environment to target coverage holes.
• Craft automated verification flows for block and chip level verification.
• Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs.
• Collaborate with other block and core level engineers to ensure a flawless verification flow.

Minimum Qualifications

• Strong knowledge of SystemVerilog and UVM
• Experience developing scalable and portable test-benches
• Experience with constrained random verification environments
• MS/BS in Computer Science or Electrical Engineering or equivalent
• Fluency in English language is required

Preferred Qualifications

• Experience defining coverage space, writing coverage model, analyzing results
• Experience with Assertion Based Verification
• Knowledge of Object Oriented Programming
• Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)
• Experience with Python, Perl or TCL
• Excellent communication and interpersonal skills combined with the ability to collaborate
• Basic knowledge of mixed signal verification